With the advent of digital signal processing (DSP), an increasing amount of radio frequency (RF) signal processing is done in the digital domain. An analog RF signal may be directly converted to a digital signal, or an analog IF signal may be converted to a digital IF signal, and subsequent DSP actions may convert the high frequency RF or IF digital signal to a lower frequency digital baseband. An analog-to-digital converter (ADC) may be used to sample an analog RF signal in order to convert the analog RF signal to a digitized signal. Downsampling or decimation may be utilized to reduce a frequency of the digitized signal to an appropriate baseband rate. In this regard, the number of samples per second in the digitized signal may be reduced by a factor N. Decimation filters may be utilized for downsampling, and a decimation filter that reduces the sampling frequency by a factor of N is referred to as a decimating-by-N filter. In addition to downsampling, a decimation filter may also be utilized to remove undesired out-of-band signals.
An advantage of having as much functionality as possible in the digital domain is that those functionalities may be implemented on a small number of chips, or even on a single chip. However, the more transistors there are on a chip, and the faster the switching speeds of the transistors, the greater the power consumption. This leads to a major problem of heat build-up on the chip, as well as concerns due to a direct cost of a larger chip size. The power consumed by the decimation filter is proportional to the frequency of the samples, and is inversely related to the width of the transition band. A transition band may comprise a band of frequencies between the pass band and the reject band. A pass band may comprise desired frequencies, and a reject band may comprise undesired frequencies that have been attenuated sufficiently that their effects on desired frequencies are negligible.
Generally, the higher the sampling rate and the narrower the transition bandwidth, the greater the power consumed by the filter. Decimation filters are, therefore, often used in stages in order to reduce the sample frequencies for the succeeding stages and because each filter only needs to proportionally reduce part of the aliasing signal. One result is a larger transition bandwidth for each filter. The slower sample frequency of the succeeding stages allow for lower power consumption by those filters, and the wider transition bandwidth also reduces power consumption. However, the additional stages of decimation filters require additional chip real estate, which leads to greater cost for the chip.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.